1. Field of the Invention:
The present invention relates to a non-volatile semiconductor memory device having a specific type of cell construction and also to a method of writing and erasing data in the memory device.
2. Description of the Prior Art:
Non-volatile semiconductor memory devices are roughly classified into two groups: a floating gate-type EEPROM (Electrically Erasable Programmable Read Only Memory) device and a MNOS (Metal Nitride Oxide Semiconductor) EEPROM device. The floating gate-type EEPROM device has now become predominant.
The floating gate-type EEPROM is described, for example, in the article, "EEPROM Starting to Change to One Transistor/Cell", in Nikkei Electronics (pp. 67 to 79, March, 1986) published by Nikkei MacGraw Hill. FIG. 2 shows one example of a known floating gate-type EEPROM.
The EEPROM has a two transistor structure. The EEPROM includes a P-type silicon substrate 1 having an N.sup.+ -type drain 2 and a source 3 on the surface thereof. Further, a select gate 4 for memory cell selection, a floating gate 5 for electric charge (electron) storage and a control gate 6 are formed through an oxide film on the surface between the drain 2 and the source 3. A tunnel oxide film 7 having a thickness of 100 angstroms or less is formed between the silicon substrate 1 and the floating gate 5 so as to enhance a charge injection efficiency. An intermediate insulating film 8 is formed over the select gate 4 and the control gate 6, and an aluminum wiring layer 9 is connected to the drain 2 through a contact hole.
The erasing and writing modes of the prior EEPROM is explained with reference to FIG. 3, which shows voltage levels applied at the time of the erasing and writing modes. It should be noted here that the erasing mode means a state where electrons are injected into the floating gate 5 to cause a high threshold voltage and that the writing mode means a state where electrons are withdrawn from the floating gate 5 to make a low threshold voltage.
At the time of the erasing mode, a high voltage V.sub.pp, e.g. 20 volts, is applied to both the select gate 4 and the control gate 6 so that the tunnel oxide film 7 has a high electric field. As a result, electrons are injected from the silicon substrate 1 into the floating gate 5. This flow of the electrons is a so-called Fowler-Nordheim (hereinafter referred to simply as FN) tunneling current.
At the time of the writing mode, the high voltage GV.sub.pp, e.g. 20 volts, is applied to the select gate 4 and to the drain 2 so as to make the tunnel oxide film 7 have a high electric field. In this case, the direction of the electric field is reversed in comparison with the case of the erasing mode, so that the electrons are emitted from the floating gate 5 into the silicon substrate 1, thereby writing data. In this manner, the EEPROM can function as a non-volatile semiconductor memory device.
However, the floating gate-type EEPROM has the following problems.
(1) Since one memory cell requires two transistors, it is difficult to shrink the cell size.
(2) Since the tunnel oxide film 7 is made of a thin oxide film of 100 angstroms or less in thickness, it is difficult to control the oxide film thickness and to form a film with good electrical properties.